View ICS663_289619.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICS663
PLL BUILDING BLOCK
Description
The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the ICS674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. The phase detector and VCO functions of the device can also be used independently. This enables the configuration of other PLL circuits. For example, the ICS663 phase detector can be used to control a VCXO circuit such as the MK3754. For applications requiring Power Down or Output Enable features, please refer to the ICS673-01.
Features
* Packaged in 8-pin SOIC * Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz *
to 120 MHz (5 V) External PLL loop filter enables configuration for a wide range of input frequencies (video Hsync, for example)
* Ability to accept an input clock in the kHz range * * * *
25 mA output drive capability at TTL levels Lower power CMOS process +3.3 V 5% or +5 V 10% operating voltage Used along with the ICS674-01, forms a complete PLL circuit independently for other PLL configurations
* Phase detector and VCO blocks can be used * Industrial temperature version available * For better jitter performance, use the MK1575
Block Diagram
LF LFR
VDD
I cp
C lock Input R E FIN P hase/ Frequency D etector
UP
F B IN
VCO
DOWN
1
MUX 4
0
2
C LK
I cp
SEL
External Feedback D ivider (such as the IC S674-01)
MDS 663 D I n t e gra te d C i r c u i t S y s t e m s
1
525 Race Stre et, San Jo se, CA 9 5126
Revision 062904 te l (40 8) 2 97-12 01
w w w. i c st . c o m
ICS663 PLL BUILDING BLOCK
Pin Assignment
VCO Post Divide Select Table SEL VCO Post Divide
8 2
FBIN VDD GND LF
1 2 3 4
8 7 6 5
REFIN CLK SEL LFR
0 1
0 = connect pin directly to ground 1 = connect pin directly to VDD
8 Pin (150 mil) SOIC
Pin Descriptions
Pin Number
1 2 3 4
Pin Name
FBIN VDD GND LF
Pin Type
Input Power Power Input
Pin Description
Feedback clock input. Connect the output of the feedback divider to this pin. Falling edge triggered. VDD. Connect to +3.3 V or +5 V. Connect to ground. Loop filter connection (refer to Figure 1 on Page 5). When using the phase detector block only, this pin serves as the charge pump output. When using the VCO block only, this pin serves as VCO input control voltage. Loop filter return (refer to Figure 1 on Page 5). Select pin for VCO post divide, as per above table. Clock output. Reference clock input. Connect the input clock to this pin. Falling edge triggered.
5 6 7 8
LFR SEL CLK REFIN
Input Input Output Input
MDS 663 D In te grated Circuit Systems
2
525 Ra ce Street, San Jose, CA 9512 6
Revision 062904 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS663 PLL BUILDING BLOCK
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS663. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Industrial Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V 0 to +70C -40 to +85C -65 to +150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
-40 +3.13
Typ.
Max.
+85 +5.5
Units
C V
DC Electrical Characteristics
VDD=3.3 V 5% or 5.0 V 10%, Ambient temperature -40 to +85C, unless stated otherwise
Parameter
Operating Voltage Logic Input High Voltage Logic Input Low Voltage LF Input Voltage Range Output High Voltage Output Low Voltage Output High Voltage, CMOS level Operating Supply Current Short Circuit Current Input Capacitance
Symbol
VDD VIH VIL VI VOH VOL VOH IDD IOS CI
Conditions
REFIN, FBIN, SEL REFIN, FBIN, SEL
Min.
3.13 2
Typ.
Max.
5.5
Units
V V
0.8 0 VDD 0.4 VDD-0.4 15 100 5
V V V V
IOH = -25 mA IOL = 25 mA IOH = -8 mA VDD = 5.0 V, No load, 40 MHz CLK SEL
2.4
mA mA pF
MDS 663 D In te grated Circuit Systems
3
525 Ra ce Street, San Jose, CA 9512 6
Revision 062904 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS663 PLL BUILDING BLOCK
AC Electrical Characteristics
VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C, unless stated otherwise
Parameter
Output Clock Frequency (from pin CLK) Input Clock Frequency (into pins REFIN or FBIN) Output Rise Time Output Fall Time Output Clock Duty Cycle Jitter, Absolute peak-to-peak VCO Gain Charge Pump Current
Symbol
fCLK fREF tOR tOF tDC tJ KO Icp
Conditions
SEL = 1 SEL = 0
Min.
1 0.25 Note 1
Typ.
Max. Units
100 25 8 MHz MHz MHz ns ns % ps MHz/V A
0.8 to 2.0V 2.0 to 0.8V At VDD/2 40
1.2 0.75 50 250 200 2.5
2 1.5 60
VDD = 5.0 V 10%, Ambient Temperature -40 to +85 C, unless stated otherwise
Parameter
Output Clock Frequency (from pin CLK) Input Clock Frequency (into pins REFIN or FBIN) Output Rise Time Output Fall Time Output Clock Duty Cycle Jitter, Absolute peak-to-peak VCO Gain Charge Pump Current
Symbol
fCLK fREF tOR tOF tDC tJ KO Icp
Conditions
SEL = 1 SEL = 0
Min.
1 0.25 Note 1
Typ.
Max. Units
120 30 8 MHz MHz MHz ns ns % ps MHz/V A
0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 45
0.5 0.5 50 150 200 2.5
1 1 55
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
150 140 120 40
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 663 D In te grated Circuit Systems
4
525 Ra ce Street, San Jose, CA 9512 6
Revision 062904 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS663 PLL BUILDING BLOCK
External Components
The ICS663 requires a minimum number of external components for proper operation. A decoupling capacitor of 0.01F should be connected between VDD and GND as close to the ICS663 as possible. A series termination resistor of 33 may be used at the clock output. Special considerations must be made in choosing loop components C1 and C2: 1) The loop capacitors should be a low-leakage type to avoid leakage-induced phase noise. For this reason, DO NOT use any type of polarized or electrolytic capacitors. 2) Microphonics (mechanical board vibration) can also induce output phase noise when the loop bandwidth is less than 1 kHz. For this reason, ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R. These and some other ceramics have piezoelectric properties that convert mechanical vibration into voltage noise that interferes with VCXO operation. For larger loop capacitor values such as 0.1F or 1F, PPS film types made by Panasonic, or metal poly types made by Murata or Cornell Dubilier are recommended. For questions or changes regarding loop filter characteristics, please contact your sales area FAE, or ICS Applications.
Avoiding PLL Lockup
In some applications, the ICS663 can "lock up" at the maximum VCO frequency. The way to avoid this problem is to use an external divider that always operates correctly regardless of the CLK output frequency. The CLK output frequency may be up to 2x the maximum Output Clock Frequency listed in the AC Electrical Characteristics above when the device is in an unlocked condition. Make sure that the external divider can operate up to this frequency.
Explanation of Operation
The ICS663 is a PLL building block circuit that includes an integrated VCO with a wide operating range. The device uses external PLL loop filter components which through proper configuration allow for low input clock reference frequencies, such as a 15.7 kHz Hsync input. The phase/frequency detector compares the falling edges of the clocks inputted to FBIN and REFIN. It then generates an error signal to the charge pump, which produces a charge proportional to this error. The external loop filter integrates this charge, producing a voltage that then controls the frequency of the VCO. This process continues until the edges of FBIN are aligned with the edges of the REFIN clock, at which point the output frequency will be locked to the input frequency.
Figure 1. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference
+3.3 or 5 V C2
0.01 F
RZ VDD
200 kH z
C1 LFR
SEL
LF
R E FIN
IC S 6 6 3
C LK
20 M H z
F B IN GND
200 kH z
100 D igital D ivider such as IC S 674-01
MDS 663 D In te grated Circuit Systems
5
525 Ra ce Street, San Jose, CA 9512 6
Revision 062904 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS663 PLL BUILDING BLOCK
Determining the Loop Filter Values
The loop filter components consist of C1, C2, and RZ. Calculating these values is best illustrated by an example. Using the example in Figure 1, we can synthesize 20 MHz from a 200 kHz input. The phase locked loop may be approximately described by the following equations:
Choosing a damping factor of 0.7 (a minimal damping factor than can be used to ensure fast lock time), damping factor equation becomes:
25, 000 200 2.5 C 1 0.7 = ----------------- -------------------------------2 200
and C1 = 1.25 nF (1.2 nF is the nearest standard value). The capacitor C2 is used to damp transients from the charge pump and should be approximately 1/20th the size of C1, i.e.,
C 2 C 1 20
Bandwidth
( R Z K O I CP ) = ----------------------------------2 N R Z K O I CP C 1 = ------ -----------------------------2 N
Damping factor,
Therefore, C2 = 60 pF (56 pF nearest standard value). To summarize, the loop filter components are: C1 = 1.2 nf C2 = 56 pf Rz = 25 k
where: KO = VCO gain (MHz/Volt) Icp = Charge pump current (A) N = Total feedback divide from VCO, including the internal VCO post divider C1 = Loop filter capacitor (Farads) RZ = Loop filter resistor (Ohms) As a general rule, the bandwidth should be at least 20 times less than the reference frequency, i.e.,
BW ( REFIN ) 20
In this example, using the above equation, bandwidth should be less than or equal to 10 kHz. By setting the bandwith to 10kHz and using the first equation, RZ can be determined since all other variables are known. In the example of Figure 1, N = 200, comprising the divide by 2 on the chip (VCO post divider) and the external divide by 100. Therefore, the bandwidth equation becomes:
R Z 200 2.5 10,000 = ------------------------------2 200
and RZ = 25 k
MDS 663 D In te grated Circuit Systems
6
525 Ra ce Street, San Jose, CA 9512 6
Revision 062904 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS663 PLL BUILDING BLOCK
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters Symbol A A1 B C D E e H h L Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
Inches Min Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
E INDEX AREA
H
12 D
A A1
h x 45 C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS663M ICS663MT ICS663MI ICS663MIT
Marking
ICS663M ICS663M ICS663MI ICS663MI
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC
Temperature
0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 663 D In te grated Circuit Systems
7
525 Ra ce Street, San Jose, CA 9512 6
Revision 062904 tel (4 08) 297-1 201
w w w. i c s t . c o m

▲Up To Search▲

Price & Availability of ICS663

	To Download ICS663 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .